Lab
5: Multiplexer
Objective
A multiplexor (mux) can be used to implement a truth table
by putting constant 1’s or 0’s into the data inputs and putting the variables
into the control (selector) lines of the mux.
The objective of this lab is to use an 8-to-1 mux
(two of them to be specific) to implement a full adder cell
(inputs: CIN, Ai, Bi, outputs: COUT,
Si) in Logisim. Use the multiplexer block provided in
Logism, there is no need to implement the logic gates inside the mux.
Assignment
This lab involves two steps, design and simulation. First, we
will design to truth table to represent our circuit. Then, we will implement
our design in Logisim.
1. Design
Start the problem by filling the truth
table for a full adder. CIN, Ai,
Bi are the full-adder inputs. Refer to the lecture notes, if necessary. COUT, Si
are the desired output of the full
adder. DI0 through DI7 are the data inputs for the multiplexer,
as labeled as A, B, C, … in the lecture slides (for example, see chap3b slide
#10). Find the correct DIi configuration (i.e. 1s and 0s) that generates
the desired COUT output pattern.
Hint: CIN,
Ai, Bi will act as our selector/control lines. You need to set the correct DI
to the desired output.
Cin
Ai
Bi
Cout
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Cin
Ai
Bi
Si
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
2. Simulation
Design a digital circuit on Logisim that has
three inputs, A, B and Cin and produces the expected output for COUT, Si. Employ the Multiplexer block (found under
Plexers) and Ground and Power blocks (found under Wiring).
For the multiplexers, you can disable the “Enable Pin” and set the “Select
Bits” to the correct number to allow for this design. Set your Data Pins option
to the correct number of bits.
Once you have the necessary components in your simulation, you can connect the
data inputs of your multiplexer to ground or power, based on your design from
part 1. Connect your variable, CIN, Ai, Bi, to the
selector input of your mux.
Label your
input and output and verify that your design works as expected.
